Hello,
I have a question related to the SPI hardware and adding more chip selects. I'm using a Pi 4B. I thought I understood what was going on, but reading more about the device tree overlays has changed my opinion on that. This post has a lot of the information I was looking for about adding additional chip selects to the SPI controller (to be used with spidev for example).
viewtopic.php?t=241191&sid=09c603470d68 ... 266a8166c8
I need more than 2 chip selects. In a current use case, I was ignoring the dedicated SPI chip selects (0.0 and 0.1) and defined some GPIOs instead that I am setting low and high myself in python before+after I use spi.writebytes(). self.CS is one of the BCM pin numberings.I was seeing that using bit-banged chip selects like this has unstable timings that are completely dependent on the cpu load. If more operations are going on, then the GPIO chip select is on for much longer than I want it to be, increasing overall SPI communication times.
I was reading about hardware vs software chip selects and that dedicated hardware chip selects will be faster since they don't have the cpu overhead slowing things down. Also, that SPI0 has dedicated SPI hardware and the other SPI busses (namely SPI1) don't.
So my question: What are the "Hardware chip selects"? If I create a new device tree overlay to add 4 chip selects to SPI0 and SPI1 each, are those hardware? Or does SPI0 only have 2 hardware chip selects (0.0 and 0.1) and adding more (0.2 and 0.3) would be software (that are now also managed by the SPI controller spidev)? Is the management by spidev via the device tree overlay what is adding performance increase?
Before I started reading about the device tree overlays I was going to add a demultiplexer to my board that I'm plugging the Raspberry Pi into. This would use the SPI0.0 chip select for all devices on the bus and route it via addressing (spi controlled shift register using SPI0.1 to set the address). But if I can just add more chip selects (that aren't slowed down by cpu load) then I'm not sure it's worth doing the IO-expansion.
Thanks for any clarification you can provide. I'm not really a software person and linux kernels are not something I'll claim to understand in the slightest.
I have a question related to the SPI hardware and adding more chip selects. I'm using a Pi 4B. I thought I understood what was going on, but reading more about the device tree overlays has changed my opinion on that. This post has a lot of the information I was looking for about adding additional chip selects to the SPI controller (to be used with spidev for example).
viewtopic.php?t=241191&sid=09c603470d68 ... 266a8166c8
I need more than 2 chip selects. In a current use case, I was ignoring the dedicated SPI chip selects (0.0 and 0.1) and defined some GPIOs instead that I am setting low and high myself in python before+after I use spi.writebytes(). self.CS is one of the BCM pin numberings.
Code:
GPIO.setmode(GPIO.BCM)GPIO.setup(self.CS, GPIO.OUT, initial=GPIO.HIGH)self.spi = spidev.SpiDev()self.spi.open(bus,device)self.spi.no_cs = True# Performing a SPI writeGPIO.output(self.CS, GPIO.LOW)self.spi.writebytes()GPIO.output(self.CS, GPIO.HIGH)I was reading about hardware vs software chip selects and that dedicated hardware chip selects will be faster since they don't have the cpu overhead slowing things down. Also, that SPI0 has dedicated SPI hardware and the other SPI busses (namely SPI1) don't.
So my question: What are the "Hardware chip selects"? If I create a new device tree overlay to add 4 chip selects to SPI0 and SPI1 each, are those hardware? Or does SPI0 only have 2 hardware chip selects (0.0 and 0.1) and adding more (0.2 and 0.3) would be software (that are now also managed by the SPI controller spidev)? Is the management by spidev via the device tree overlay what is adding performance increase?
Before I started reading about the device tree overlays I was going to add a demultiplexer to my board that I'm plugging the Raspberry Pi into. This would use the SPI0.0 chip select for all devices on the bus and route it via addressing (spi controlled shift register using SPI0.1 to set the address). But if I can just add more chip selects (that aren't slowed down by cpu load) then I'm not sure it's worth doing the IO-expansion.
Thanks for any clarification you can provide. I'm not really a software person and linux kernels are not something I'll claim to understand in the slightest.
Statistics: Posted by iLikePiGuy — Wed Sep 17, 2025 9:43 pm — Replies 0 — Views 72