I had originally wanted to pursue a supercap-based UPS for providing shutdown functionality on a loss of power. That decision was based on the needs for something robust, compact, and easy to integrate into my existing PCB.
The primary hurdle is the charge time (of the capacitors) which could be decreased with a battery-based solution that wouldn't require a constant charge/discharge but that would require a larger physical footprint. An additional alternative would be re-arranging the topology of the supercapacitors but that also has tradeoffs with conversion efficiencies, etc. In the end, I decided that simply changing my filesystem to be an "overlayfs" and function in read-only would be the better option. Because I don't need any write permissions for my application, this project solidified that any UPS (supercap or otherwise) would be an increase in complexity and cost to the overall design.
That being said it was a fun/interesting project and I've seen a few supercapacitor based discussions pop up here so I at least wanted to share my findings and knowledge! This is all based on my specific application with a CM4, so YMMV but changing some of the inputs/constraints could be tailored to whatever the application is.
For choosing the UPS, there are some tradeoffs/considerations that come into play between a more traditional LiPo/LiOn based "battery" backup and a supercapacitor UPS. I won't go into great detail but for me this really came down to the following:
Battery-based
Both of those gave me an estimated 500mA load (since I wasn't expected to be at full-load even normally functioning) and a voltage drop threshold of 1V. With that in mind, using the venerable [I = C dv/dt] gave me my starting parameters. For an expected 20s "window" for the shutdown, an approximate 10F capacitance was required; great, this is pretty easy to come across. Using the same equation, to charge from a dead 0V on the capacitor it was expected to take about 33s.
I did a preliminary estimation in LTspice just to get an idea of what I was working with. Input V1 is configured as a 12VDC output for approx. 40s and then turn off to 0VDC, simulating a loss of power. Resistor R2 functions as a dummy-load to represent a 500mA load. This is not perfect as it does not represent a constant current load but will suffice for benchmark testing . U5 functions as the “normal” supply that supplies power under typical conditions and U4 functions as the “charging” supply for the supercapacitor. Ideal diode D3 represents a power supply switch that transfers to the supercapacitor supply on loss of power from V1.
![Image]()
Since the simulation is just as simplified as the hand calcs (vs. "real world") the expected charge time and discharge time were similar to the simply capacitor equation from before.
![Image]()
With all this in mind, I made a custom PCB with the intended various components of the final circuit along with provisions for testing the various elements of the design. Resistors R1, R2, and R4 are 10mOhm resistors to be used for current measurement. Protective diodes D1 and D2 prevent back-feeding through the voltage regulators. U5 is a current-limiting IC used typically in USB power output applications that's intended to limit charge current when the capacitor is empty, so not to over-limit U2. U5 is an ideal diode IC specifically for “hot-swapping” power supplies. When the voltage at the CE pin (3) is 250mV less than the voltage at the Vin pin (1) an internal FET is on, and the ST pin (5) is high-impedance. This effectively supplies Vout pin (5) with the voltage from Vin. When the voltage at the CE pin is 80mV greater than the voltage at Vin, the internal FET is off and the ST pin is driven to ground, which turns on Q1. The voltage divider of R7 and R8 ensures that under normal conditions the voltage at the CE pin is below this threshold. Currently a ratio of 10R8 = R7 is used which drops the voltage by approximately 450mV. For a tighter threshold, a ratio of 17R8 = R7 could be used for a 230mV drop. Lastly, U4 is a supercapacitor specific cell balancing IC that ensures when charging two capacitors in series, that the voltage remains constant between them (thus, not exceeding their individual ratings).
![Image]()
The layout itself is pretty simple. That damn ideal diode was a pain to get soldered lol! I didn't make a stencil so it required some post-cleanup after the hot-air gun got everything flowed. Also that frickin capacitor balancer didn't have the typical "notch" or "dot" so i spent a while second-guessing myself on which side was the "chamfered" edge but I did get it right.
****One important note here. R7/R8 are not shown in the layout since this is from an earlier revision. I had to bodge those in after the fact. That's what happens when you don't read the datasheet and completely understand it like a good designer.... "oh its got examples, what's the worst that can happen?"
![Image]()
After getting the board and ordering the parts, I got everything assembled. Before adding the capacitors I did some static testing by omitting the current sense resistor for the "normal" supply and wiring in a switch in it's place to simulate a loss of power. That's when I found my oopsie for the ideal diode IC and fixed it. After that, the capacitors got added and I started some testing. Here's the complete board with it's bodge job in all it's glory.
![Image]()
Also, unsure of the effects should one of the capacitors go awry, I implemented a very hi-tech blast shield![:lol:]( "Laughing")
Here you can also see the two DMM's I'm using to monitor output voltage as well as charge current.
![Image]()
The tested times for discharge closely match those from the theoretical calculations and simulated results. The large difference in the total charging time can be attributed to the input current while charging. While not specifically recorded, the input current was found to never exceed 800mA at peak, often functioning around 500-600mA. Given the correlation of the discharge time, if further testing and circuit refinement was performed to increase the charge rate it is expected that the tested charge time would have a similar correlation to the calculated and simulated charge times.
![Image]()
And that's it! Like I said at first, this would be a viable option for most "normal" cases. The specific application is for a car dash I'm designing/migrating from an atmega328 (arduino) into the pi universe. This was one of the "last" things I was working on for the PCB in addition to the work I'm doing on the operating system. The one edge case I'm worried about is if there's a quick power cycle, like someone turns the power on and then decides to turn it back off again. To make things as robustly as I can, it just makes the most sense to use a read-only "overlayfs" approach which then completely negates the need for a UPS. So kinda sucks that it won't get used but it was still a great exercise and was fun taking it from conception to test.
The primary hurdle is the charge time (of the capacitors) which could be decreased with a battery-based solution that wouldn't require a constant charge/discharge but that would require a larger physical footprint. An additional alternative would be re-arranging the topology of the supercapacitors but that also has tradeoffs with conversion efficiencies, etc. In the end, I decided that simply changing my filesystem to be an "overlayfs" and function in read-only would be the better option. Because I don't need any write permissions for my application, this project solidified that any UPS (supercap or otherwise) would be an increase in complexity and cost to the overall design.
That being said it was a fun/interesting project and I've seen a few supercapacitor based discussions pop up here so I at least wanted to share my findings and knowledge! This is all based on my specific application with a CM4, so YMMV but changing some of the inputs/constraints could be tailored to whatever the application is.
For choosing the UPS, there are some tradeoffs/considerations that come into play between a more traditional LiPo/LiOn based "battery" backup and a supercapacitor UPS. I won't go into great detail but for me this really came down to the following:
Battery-based
- More commercially available
- Longer backup time
- Larger footprint
- Easier to integrate
- Smaller footprint
- More robust
- I,idle ~ 400mA
- I,full load ~ 1400mA
- I,shutdown (standby) ~8ma
Both of those gave me an estimated 500mA load (since I wasn't expected to be at full-load even normally functioning) and a voltage drop threshold of 1V. With that in mind, using the venerable [I = C dv/dt] gave me my starting parameters. For an expected 20s "window" for the shutdown, an approximate 10F capacitance was required; great, this is pretty easy to come across. Using the same equation, to charge from a dead 0V on the capacitor it was expected to take about 33s.
I did a preliminary estimation in LTspice just to get an idea of what I was working with. Input V1 is configured as a 12VDC output for approx. 40s and then turn off to 0VDC, simulating a loss of power. Resistor R2 functions as a dummy-load to represent a 500mA load. This is not perfect as it does not represent a constant current load but will suffice for benchmark testing . U5 functions as the “normal” supply that supplies power under typical conditions and U4 functions as the “charging” supply for the supercapacitor. Ideal diode D3 represents a power supply switch that transfers to the supercapacitor supply on loss of power from V1.
Since the simulation is just as simplified as the hand calcs (vs. "real world") the expected charge time and discharge time were similar to the simply capacitor equation from before.
With all this in mind, I made a custom PCB with the intended various components of the final circuit along with provisions for testing the various elements of the design. Resistors R1, R2, and R4 are 10mOhm resistors to be used for current measurement. Protective diodes D1 and D2 prevent back-feeding through the voltage regulators. U5 is a current-limiting IC used typically in USB power output applications that's intended to limit charge current when the capacitor is empty, so not to over-limit U2. U5 is an ideal diode IC specifically for “hot-swapping” power supplies. When the voltage at the CE pin (3) is 250mV less than the voltage at the Vin pin (1) an internal FET is on, and the ST pin (5) is high-impedance. This effectively supplies Vout pin (5) with the voltage from Vin. When the voltage at the CE pin is 80mV greater than the voltage at Vin, the internal FET is off and the ST pin is driven to ground, which turns on Q1. The voltage divider of R7 and R8 ensures that under normal conditions the voltage at the CE pin is below this threshold. Currently a ratio of 10R8 = R7 is used which drops the voltage by approximately 450mV. For a tighter threshold, a ratio of 17R8 = R7 could be used for a 230mV drop. Lastly, U4 is a supercapacitor specific cell balancing IC that ensures when charging two capacitors in series, that the voltage remains constant between them (thus, not exceeding their individual ratings).
The layout itself is pretty simple. That damn ideal diode was a pain to get soldered lol! I didn't make a stencil so it required some post-cleanup after the hot-air gun got everything flowed. Also that frickin capacitor balancer didn't have the typical "notch" or "dot" so i spent a while second-guessing myself on which side was the "chamfered" edge but I did get it right.
****One important note here. R7/R8 are not shown in the layout since this is from an earlier revision. I had to bodge those in after the fact. That's what happens when you don't read the datasheet and completely understand it like a good designer.... "oh its got examples, what's the worst that can happen?"
After getting the board and ordering the parts, I got everything assembled. Before adding the capacitors I did some static testing by omitting the current sense resistor for the "normal" supply and wiring in a switch in it's place to simulate a loss of power. That's when I found my oopsie for the ideal diode IC and fixed it. After that, the capacitors got added and I started some testing. Here's the complete board with it's bodge job in all it's glory.
Also, unsure of the effects should one of the capacitors go awry, I implemented a very hi-tech blast shield
Here you can also see the two DMM's I'm using to monitor output voltage as well as charge current.
The tested times for discharge closely match those from the theoretical calculations and simulated results. The large difference in the total charging time can be attributed to the input current while charging. While not specifically recorded, the input current was found to never exceed 800mA at peak, often functioning around 500-600mA. Given the correlation of the discharge time, if further testing and circuit refinement was performed to increase the charge rate it is expected that the tested charge time would have a similar correlation to the calculated and simulated charge times.
- Charge time of 30s (theoretical) vs 38s (simulated) vs 85s (tested)
- Discharge time 20s (theoretical) vs 21s (simulated) vs 22s (tested)
And that's it! Like I said at first, this would be a viable option for most "normal" cases. The specific application is for a car dash I'm designing/migrating from an atmega328 (arduino) into the pi universe. This was one of the "last" things I was working on for the PCB in addition to the work I'm doing on the operating system. The one edge case I'm worried about is if there's a quick power cycle, like someone turns the power on and then decides to turn it back off again. To make things as robustly as I can, it just makes the most sense to use a read-only "overlayfs" approach which then completely negates the need for a UPS. So kinda sucks that it won't get used but it was still a great exercise and was fun taking it from conception to test.
Statistics: Posted by jungle_jim — Sun Jan 21, 2024 11:13 pm — Replies 0 — Views 129