Why does the RP2040 violate the will of the Cortex-M0+ with the SIO module? How does the RP2040 manage the AHB-lite vs IOPORT in terms of write order?
In many ways it would have been safer to use GPIO port remotely off AHB-lite. Honestly I think it would have been better to use Cortex-M0 with three stage pipeline.
In many ways it would have been safer to use GPIO port remotely off AHB-lite. Honestly I think it would have been better to use Cortex-M0 with three stage pipeline.
Statistics: Posted by dthacher — Sat Jun 21, 2025 7:32 pm — Replies 2 — Views 93